An analog-digital converting device converts an analog signal into a digital signal, and a pipelined analog-digital converting device is formed of a plurality of such analog-digital converting devices connected to one another. FIG. 1 is a block diagram of a conventional pipelined analog-digital converting device 101. Referring to FIG. 1, the conventional pipelined analog-digital converting device 101 includes first through nth sub analog-digital converters 111a through 111n, first through nth multiplying digital to analog converters (MDACs) 121a through 121n, and a sample/hold amplifier 131. All of the first through nth sub analog-digital converters 111a through 111n, which may be flash analog-digital converters, and the first through nth MDACs 121a through 121n, use one reference voltage Vref. In other words, the first through nth sub analog-digital converters 111a through 111n, and the first through nth MDACs 121a through 121n receive the reference voltage Vref supplied by a reference voltage generator (not shown).
FIG. 2 illustrates waveforms of signals transmitted to the pipelined analog-digital converting device 101 of FIG. 1 and consequent operations of some elements of the pipelined analog-digital converting device 101. In FIG. 2, S.S, S.H, R.S, S.C, and S.A are abbreviations for signal sampling, signal holding, reference sampling, signal comparing, and signal amplifying, respectively. Referring to FIG. 2, while a clock signal CK is at a high level (tk1), the first sub analog-digital converter 111a samples an analog signal A1 output from the sample/hold amplifier 131 of FIG. 1. At this time, the first MDAC 121a of FIG. 1 samples the reference voltage Vref. While the clock signal CK is at the high level (tk1), the first sub analog-digital converter 111a samples the reference voltage Vref and the first MDAC 121a amplifies the analog signal A1.
When the reference voltage Vref is applied to the pipelined analog-digital converting device 101, the reference voltage Vref is stabilized at a constant level after some fluctuations during each clock cycle. When the operating frequency of the pipelined analog-digital converting device 101 is high, all operations are performed while the reference voltage Vref fluctuates. Such fluctuations of the reference voltage Vref may cause errors in the first through nth MDACs 121a through 121n, whose precision is required. To prevent such errors, the operating frequency of the pipelined analog-digital converting device 101 can be lowered.
In order to use a reference voltage that does not fluctuate, at a high operating frequency, a large capacity reference voltage generator may be used, resulting in an increase in the size of the reference voltage generator and high manufacturing costs. The reference voltage generator may be connected to a large external capacitor through a pin at the analog-digital converting device 101 and the reference voltage Vref generated by the reference voltage generator may be supplied to the capacitor. However, in this case, a dedicated pin is additionally required.